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Implementation Hints
9
Clocking
CorePCIF supports generating the PCI clock when the FPGA is also the main bus control function. It is important that
the clock networks be configured correctly to allow the core to meet the PCI setup and hold times, as well as to avoid
internal clock skew.
When generating the PCI clock, the clock source should be connected to the CLK_IN port. This is then routed to the
PCI clock pad to drive the PCI bus, and driven back into the core using a global network. This global network on the
CLK_OUT port should be used to clock the rest of the FPGA logic running off the PCI clock network ( Figure 9-1 ).
GENERATE_PCICLK
CLK_IN
CLK_OUT
ENB
CLKBUF
PCI BUS
CLOCK
A
D
A
D
A
D
Q 1
Q 1
A
Q 1
Q 1
D
Q 4
Figure 9-1 · Clock Generation
Clocking in SmartFusion2
In the SmartFusion2 device, when using 66 MHz configuration, the CorePCIF PCI CLK input signal should be driven
by a Fabric CCC (FCCC). You must instantiate the FCC in the top-level design and use the external CLK input as a
reference clock. This is to ensure that external setup and clock to out timing are met in the design.
Note: The data paths (for example, AD) use registers to drive the output and you need to use IO-REG combining for
these register outputs.
Figure 9-2 shows the clock-to-out path in SmartFusion2, which has a requirement of 6ns (as part of the PCIF standard.
In the SmartFusion2 device, the sum of UPAD, UGB, and URGB on the clock input is around 3ns, if you use the IO
bank as shown in “Pin Assignments” section on page 129 . The output pad delay is roughly 2.5ns. This leaves only
around 500ps to route and register the output internally. This does not allow enough margin to achieve timing closure in
most cases.
Figure 9-2 · Clocking in SmartFusion2 with No CCC
v4.0
127
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